Intel’s Atom Redesign Aimed at Datacenters, Devices

Intel formally announced the next generation of its Atom architecture on May 6. Known as “Silvermont,” the microarchitecture will be used as the foundation of everything from tablets to servers to in-car entertainment systems.

In the context of the server, the Silvermont architecture forms the underpinnings of Avoton, the Atom-based chip that’s due in the second half of 2013. Intel didn’t release the clock speeds or power numbers for the new architecture, with executives saying they preferred to release them on a case-by-case basis.

Over the past few years, CPU design has moved to a System-on-a-Chip (SoC) model, with the core CPU surrounded by peripheral logic—and within the PC, the graphics core as well. The Atom has used that same model, with products for various markets relying on the same Atom core—Silvermont is designed for two to eight cores—as well as the process technology, which on Silvermont will be 22 nanometers. Intel defines each product (Rangeley for switches, Avoton for microservers, and Bay Trail for low-end PCs) by the number of cores and the peripheral logic. Perhaps more importantly, Silvermont also includes a tightly coupled L2 cache as well as a “IDI” point-to-point interface to the SOC fabric.

The idea is to build a balanced system, not just a great core, said Belli Kutana, an Intel fellow and member of the Intel Architecture Group. It’s a strategy that Intel has had for several years, but has refined over time within its various product groups.

The Silvermont architecture represents the first significant redesign of the Atom architecture in about five years, since its inception. The X86-compatible core design is being ported to Intel’s “tick-tock” model, where more frequent architectural updates will be interspersed with improvements in process technology; next up, for example, is the “Airmont” 14-nm refresh, which will occur sometime in the future.

Intel took pains to indicate that it had combined both microarchitectural improvements as well as the process shrink to both improve performance and save power; from a benchmark perspective, Silvermont will offer between twice and 2.5x the performance of the prior-generation Saltwell chips, as well as offer a 4.5x (or so) power reduction, Intel said. That’s roughly the same advantage that Intel touted over competitors in the tablet space, based upon current and expected designs.

The specific improvements within Silvermont include process improvements such as 3D transistors, a metal stack that’s been optimized for use with Intel’s own intellectual property, along with custom arrays and libraries tailored to take advantage of the Silvermont’s redesign. Silvermont runs an out-of-order execution pipeline, with improved instruction latencies, more efficient branch processing and recovery, and lower-latency caches.

Silvermont can also take up to three simple instructions and “fuse” them together, eliminating extra cost on improving the pipeline, Kutana said. From a power and performance perspective, the idea is to get done what needs doing, and quickly shut down into a low-power sleep mode.

However, if additional performance is needed, Silvermont also includes improvements in “burst mode,” where the chip can allocate the thermal budget to other elements of the SOC, including graphics, instead of overclocking a single CPU core. (This might not be that important within a server, but might make a significant difference within a PC or tablet.)

 

Image: Intel

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